More sophisticated technology has created a heightened demand for smaller, faster semiconductor devices incorporating an ever increasing number of components. An area of special interest is semiconductor memory devices, such as a random access memory ("RAM"), having greater storage capacity.
Such memory devices typically include a number of memory cells accessed by a pass transistor coupled to at least one bit line. The memory cells often include at least one storage device coupled to a storage node. Generally, memory cells include two storage devices, such as storage transistors, each coupled to one of a pair of complementary storage nodes which are accessed by two pass transistors. Each pass transistor is further coupled to a bit line. Thus, each memory cell is often located between two complementary bit lines.
The pass transistors have gate electrodes coupled to a word line. A signal, such as an address or SELECT signal, is provided on the word line associated with the memory cell to select or access the memory cell. Once selected via the word line, the memory cell can be read or written to through the pass transistors via the bit lines.
To increase the storage capacity of such memory devices, a greater number of individual memory cells, as well as the additional components required to access the added cells, must be incorporated. Because available area within a memory device is at a premium, the physical layout of the components must become more compact and the physical dimensions of each component must be decreased to prevent the overall dimensions of the memory device from becoming excessively large.
The need to optimize the use of available physical area is especially critical in static RAM devices in which a typical memory cell includes four transistors accessed by two pass transistors coupled between a pair of complementary bit lines. Accordingly, a need exists for innovative physical layouts of individual components such that space optimization may be accomplished.